ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS (Cont’d)
When selecting the DMA transaction with memory,
bit DCPR.RM (bit 0 of DCPR) must be cleared.
When the Interrupt Pending (IP) bit is set by a
hardware event (or by software), and the DMA
Mask bit (DM) is set, a DMA request is generated.
If the Priority Level of the DMA source is higher
than, or equal to, the Current Priority Level (CPL),
the DMA transfer is executed at the end of the cur-
rent instruction. DMA transfers read/write data
from/to the location pointed to by the DMA Ad-
dress Register, the DMA Address register is incre-
mented and the Transaction Counter Register is
decremented. When the contents of the Transac-
tion Counter are decremented to zero, the DMA
Mask bit (DM) is cleared and an interrupt request
is generated, according to the Interrupt Mask bit
(End of Block interrupt). This End-of-Block inter-
rupt request is taken into account, depending on
the PRL value.
To selectbetween using theISR orthe DMASR reg-
ister to extend the address, (see Memory Manage-
ment Unit chapter), the control bit DAPR.PS (bit 0
of DAPR) must be cleared or set respectively.
The DMA transaction Counter must be initialized
with the number of transactions to perform and will
be decremented after each transaction. The DMA
Address must be initialized with the starting ad-
dress of the DMA table and is increased after each
transaction. These two registers must be located
between addresses 00h and DFh of the Register
File.
Once a DMA channel is initialized, a transfer can
start. The direction of the transfer is automatically
defined by the type of peripheral and programming
mode.
WARNING. DMA requests are not acknowledged
if the top level interrupt service is in progress.
Once the DMA table is completed (the transaction
counter reaches 0 value), an Interrupt request to
the CPU is generated.
Figure 30. DMA Between Memory and Peripheral
IDCR
IVR
DMA TRANSACTION
DAPR
DCPR
FFh
PAGED
DATA
REGISTERS
F0h
EFh
PERIPHERAL
PAGED REGISTERS
DMA
TABLE
SYSTEM
DATA
ALREADY
REGISTERS
TRANSFERRED
E0h
DFh
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DMA
TRANSACTION
COUNTER
0100h
0000h
DMA
VECTOR
TABLE
ADDRESS
ISR ADDRESS
MEMORY
REGISTER FILE
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