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ST90135M6 参数 Datasheet PDF下载

ST90135M6图片预览
型号: ST90135M6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16号位微控制器( MCU ), 16至64K的ROM 。 OTP或EPROM 。 512 2K的RAM - ST9 +系列\n [8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY ]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 199 页 / 2805 K
品牌: ETC [ ETC ]
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ST90158 - INTERRUPTS  
4.9 INTERRUPT RESPONSE TIME  
cycles (DIVWS and MUL instructions) or 49 for  
other instructions.  
The interrupt arbitration protocol functions com-  
pletely asynchronously from instruction flow and  
requires 5 clock cycles. One more CPUCLK cycle  
is required when an interrupt is acknowledged.  
Requests are sampled every 5 CPUCLK cycles.  
For a non-maskable Top Level interrupt, the re-  
sponse time between a user event and the start of  
the interrupt service routine can range from a min-  
imum of 22 clock cycles to a maximum of 51 clock  
cycles (DIV instruction), 49 clock cycles (DIVWS  
and MUL instructions) or 45 for other instructions.  
If the interrupt request comes from an external pin,  
the trigger event must occur a minimum of one  
INTCLK cycle before the sampling time.  
In order to guarantee edge detection, input signals  
must be kept low/high for a minimum of one  
INTCLK cycle.  
When an arbitration results in an interrupt request  
being generated, the interrupt logic checks if the  
current instruction (which could be at any stage of  
execution) can be safely aborted; if this is the  
case, instruction execution is terminated immedi-  
ately and the interrupt request is serviced; if not,  
the CPU waits until the current instruction is termi-  
nated and then services the request. Instruction  
execution can normally be aborted provided no  
write operation has been performed.  
An interrupt machine cycle requires a basic 18 in-  
ternal clock cycles (CPUCLK), to which must be  
added a further 2 clock cycles if the stack is in the  
Register File. 2 more clock cycles must further be  
added if the CSR is pushed (ENCSR =1).  
The interrupt machine cycle duration forms part of  
the two examples of interrupt response time previ-  
ously quoted; it includes the time required to push  
values on the stack, as well as interrupt vector  
handling.  
For an interrupt deriving from an external interrupt  
channel, the response time between a user event  
and the start of the interrupt service routine can  
range from a minimum of 26 clock cycles to a max-  
imum of 55 clock cycles (DIV instruction), 53 clock  
In Wait for Interrupt mode, a further cycle is re-  
quired as wake-up delay.  
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