ST90158 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 26. External Interrupts Control Bits and Vectors
n
Watchdog/Timer
End of count
IA0S
TEA0
V6
V7
V5 V4 0
0
0
0
VECTOR
Priority level
“0”
PL2A PL1A
0
INT A0
request
Mask bit
Pending bit IPA0
IMA0
“1”
INT 0 pin
INT 1 pin
*
TEA1
V6
V5 V4 0
V7
0
0
1
VECTOR
Priority level
PL2A PL1A
INT A1
request
1
Mask bit
Pending bit IPA1
IMA1
SPEN,BMS
SPI Interrupt
TEB0
V6
V5 V4 0
V7
PL2B PL1B
1
0
0
VECTOR
Priority level
0
INT B0
request
“0,0”
Mask bit
Pending bit IPB0
INT 2 pin
INT 3 pin
IMB0
*
TEB1
V6
V7
V5 V4 0
1
0
1
VECTOR
Priority level
PL2B PL1B
INT B1
request
1
Mask bit
IMB1
Pending bit IPB1
INTS
“0”
TEC0
STD Timer
V6
V7
V5 V4 1
0
0
0
VECTOR
Priority level
INT C0
request
PL2C PL1C
0
INT 4 pin
“1”
Pending bit IPC0
Mask bit
IMC0
*
TEC1
V6
V7
V5 V4 1
0
0
1
VECTOR
Priority level
INT C1
request
PL2C PL1C
1
INT 5 pin
Pending bit IPC1
Mask bit
IMC1
INT_SEL
“1”
RCCU
TED0
V6
V7
V5 V4 1
1
0
0
VECTOR
Priority level
PL2D PL1D
0
INT D0
request
INT 6 pin
INT 7 pin
“0”
Mask bit
IMD0
Pending bit IPD0
*
TED1
V6
V4
1
1
V7
V5
0
1
VECTOR
Priority level
INT D1
request
PL2D PL1D
1
Mask bit
IMD1
Pending bit IPD1
*
Shared channels, see warning
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9
ETC [ ETC ]
