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ST72254G1B1 参数 Datasheet PDF下载

ST72254G1B1图片预览
型号: ST72254G1B1
PDF下载: 下载PDF文件 查看货源
内容描述: 与单电压闪存的8位MCU 。 ADC。 16位定时器。 SPI 。\n [8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY. ADC. 16-BIT TIMERS. SPI. ]
分类和应用: 闪存
文件页数/大小: 140 页 / 1350 K
品牌: ETC [ ETC ]
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ST72104G, ST72215G, ST72216G, ST72254G  
16-BIT TIMER (Cont’d)  
16-bit Read Sequence: (from either the Counter  
Register or the Alternate Counter Register).  
Clearing the overflow interrupt request is done in  
two steps:  
1. Reading the SR register while the TOF bit is set.  
2. An access (read or write) to the CLR register.  
Beginning of the sequence  
Read  
LS Byte  
is buffered  
Note: The TOF bit is not cleared by accessing the  
ACLR register. The advantage of accessing the  
ACLR register rather than the CLR register is that  
it allows simultaneous use of the overflow function  
and reading the free running counter at random  
times (for example, to measure elapsed time) with-  
out the risk of clearing the TOF bit erroneously.  
MS Byte  
At t0  
Other  
instructions  
Returns the buffered  
LS Byte value at t0  
Read  
LS Byte  
At t0 +t  
The timer is not affected by WAIT mode.  
In HALT mode, the counter stops counting until the  
mode is exited. Counting then resumes from the  
previous count (MCU awakened by an interrupt) or  
from the reset count (MCU awakened by a Reset).  
Sequence completed  
The user must read the MS Byte first, then the LS  
Byte value is buffered automatically.  
This buffered value remains unchanged until the  
16-bit read sequence is completed, even if the  
user reads the MS Byte several times.  
12.2.3.2 External Clock  
The external clock (where available) is selected if  
CC0=1 and CC1=1 in the CR2 register.  
After a complete reading sequence, if only the  
CLR register or ACLR register are read, they re-  
turn the LS Byte of the count value at the time of  
the read.  
The status of the EXEDG bit in the CR2 register  
determines the type of level transition on the exter-  
nal clock pin EXTCLK that will trigger the free run-  
ning counter.  
Whatever the timer mode used (input capture, out-  
put compare, One Pulse mode or PWM mode) an  
overflow occurs when the counter rolls over from  
FFFFh to 0000h then:  
The counter is synchronised with the falling edge  
of the internal CPU clock.  
A minimum of four falling edges of the CPU clock  
must occur between two consecutive active edges  
of the external clock; thus the external clock fre-  
quency must be less than a quarter of the CPU  
clock frequency.  
– The TOF bit of the SR register is set.  
– A timer interrupt is generated if:  
– TOIE bit of the CR1 register is set and  
– I bit of the CC register is cleared.  
If one of these conditions is false, the interrupt re-  
mains pending to be issued as soon as they are  
both true.  
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