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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
9.2.15 CLOCK ARBITRATION  
9.2.16 SLEEP OPERATION  
2
Clock arbitration occurs when the master, during any  
receive, transmit, or repeated start/stop condition,  
deasserts the SCL pin (SCL allowed to float high).  
When the SCL pin is allowed to float high, the baud rate  
generator (BRG) is suspended from counting until the  
SCL pin is actually sampled high. When the SCL pin is  
sampled high, the baud rate generator is reloaded with  
the contents of SSPADD<6:0> and begins counting.  
This ensures that the SCL high time will always be at  
least one BRG rollover count in the event that the clock  
is held low by an external device (Figure 9-18).  
While in sleep mode, the I C module can receive  
addresses or data, and when an address match or  
complete byte transfer occurs, wake the processor from  
sleep (if the SSP interrupt is enabled).  
9.2.17 EFFECTS OF A RESET  
A reset disables the SSP module and terminates the  
current transfer.  
FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE  
BRG overflow,  
Release SCL,  
If SCL = 1 Load BRG with  
SSPADD<6:0>, and start count  
to measure high time interval  
BRG overflow occurs,  
Release SCL, Slave device holds SCL low.  
SCL = 1 BRG starts counting  
clock high interval.  
SCL  
SDA  
SCL line sampled once every machine cycle (TOSC 4).  
Hold off BRG until SCL is sampled high.  
TBRG  
TBRG  
TBRG  
1999 Microchip Technology Inc.  
DS30292B-page 87  
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