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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
9.2.14 STOP CONDITION TIMING  
while SCL is high, the P bit (SSPSTAT<4>) is set. A  
TBRG later, the PEN bit is cleared and the SSPIF bit is  
set (Figure 9-17).  
A stop bit is asserted on the SDA pin at the end of a  
receive/transmit by setting the Stop Sequence Enable  
bit PEN (SSPCON2<2>). At the end of a receive/trans-  
mit, the SCL line is held low after the falling edge of the  
ninth clock. When the PEN bit is set, the master will  
assert the SDA line low . When the SDA line is sam-  
pled low, the baud rate generator is reloaded and  
counts down to 0. When the baud rate generator times  
out, the SCL pin will be brought high, and one TBRG  
(baud rate generator rollover count) later, the SDA pin  
will be deasserted. When the SDA pin is sampled high  
Whenever the firmware decides to take control of the  
bus, it will first determine if the bus is busy by checking  
the S and P bits in the SSPSTAT register. If the bus is  
busy, then the CPU can be interrupted (notified) when  
a Stop bit is detected (i.e. bus is free).  
9.2.14.1 WCOL STATUS FLAG  
If the user writes the SSPBUF when a STOP sequence  
is in progress, then WCOL is set and the contents of the  
buffer are unchanged (the write doesn’t occur).  
FIGURE 9-17: STOP CONDITION RECEIVE OR TRANSMIT MODE  
SCL = 1 for TBRG, followed by SDA = 1 for TBRG  
after SDA sampled high. P bit (SSPSTAT<4>) is set  
Write to SSPCON2  
Set PEN  
PEN bit (SSPCON2<2>) is cleared by  
hardware and the SSPIF bit is set  
Falling edge of  
9th clock  
TBRG  
SCL  
ACK  
SDA  
P
TBRG  
TBRG  
TBRG  
SCL brought high after TBRG  
SDA asserted low before rising edge of clock  
to setup stop condition.  
Note: TBRG = one baud rate generator period.  
DS30292B-page 86  
1999 Microchip Technology Inc.  
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