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LXT350PE 参数 Datasheet PDF下载

LXT350PE图片预览
型号: LXT350PE
PDF下载: 下载PDF文件 查看货源
内容描述: PCM收发器|单| CEPT PCM - 30 / E - 1 | CMOS | LDCC | 28PIN |塑料\n [PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC ]
分类和应用: 电信集成电路PC
文件页数/大小: 50 页 / 1130 K
品牌: ETC [ ETC ]
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T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation LXT350  
2.7.1.4  
Dual Loopback (DLOOP)  
See Figure 9. In Hardware mode, DLOOP is selected by setting both the RLOOP and LLOOP pins  
High. In Host mode set bits CR2.ERLOOP = 1 and CR2.ELLOOP = 1. In DLOOP mode, the  
transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter  
Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered  
from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter  
attenuation.  
Figure 9. Dual Loopback  
2.7.2  
Internal Pattern Generation  
2.7.2.1  
Transmit All Ones (TAOS)  
See Figure 10. When TAOS is active, the transceiver ignores the TPOS and TNEG inputs and  
transmits a continuous stream of 1s at the TCLK frequency. When TCLK is not supplied, TAOS  
timing is derived from MCLK. This can be used as the Alarm Indication Signal (AISalso called  
the Blue Alarm).  
Both TAOS and LLOOP can operate simultaneously as shown in Figure 5, however, RLOOP  
inhibits TAOS. When both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to  
RCLK and RPOS/RNEG (through the jitter attenuator if enabled), and the all ones pattern is also  
routed to TTIP/TRING.  
In Host mode, TAOS is activated when bit CR2.ETAOS = 1. In Hardware mode, setting the TAOS  
pin High activates TAOS.  
Figure 10. TAOS Data Path  
2.7.2.2  
Quasi-Random Signal Source (QRSS)  
See Figure 11. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 220-1 pseudo-  
random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is  
215-1 PRBS with inverted output.  
Datasheet  
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