LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
CODEV detection is not available in Hardware mode. In Host mode, HDB3 code violation
detection is enabled when the HDB3 encoders/decoders are enabled. This requires that
CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select CODEV
detection, set bit CR4.CODEV = 1.
2.7.3.6
HDB3 Zero Substitution Violation Detection (ZEROV)
An HDB3 ZEROV is the receipt of four or more consecutive zeros. This does not occur with
correctly encoded HDB3 data unless there are transmission errors. The BPV pin goes High for a
full RCLK cycle to report a ZEROV. Note that when ZEROV detection enabled, the BPV pin will
also indicate received BPVs and CODEVs, if these detection options are enabled.
ZEROV detection is not available in Hardware mode. In Host mode, HDB3 zero substitution
violation (ZEROV) detection is enabled when the HDB3 encoders/decoders are enabled. This
requires CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select
ZEROV detection, set bit CR4.ZEROV = 1.
2.7.4
Alarm Condition Monitoring
2.7.4.1
Loss of Signal (LOS)
The Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI 300233. The
receiver LOS monitor loads a digital counter at the RCLK frequency. The count increments with
each received 0 and the counter resets to 0 on receipt of a 1. When the count reaches “n” 0s, the
LOS flag goes High, and the MCLK replaces the recovered clock at the RCLK output in a smooth
transition. For Hardware mode T1 operations, the number of 0s, n = 175, and for Hardware mode
E1 operations, n = 32. In Host mode, either number can be changed to 2048 by setting bit
CR4.LOS2048 to 1.
For T1 operation, when the received signal has 12.5% 1’s density (16 marks in a sliding 128-bit
period, with fewer than 100 consecutive 0s), the LOS flag returns Low and the recovered clock
replaces MCLK at the RCLK output in another smooth transition.
For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1’s density
(four 1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 Host mode operation,
the out-of-LOS criterion can be modified from 12.5% marks density to 32 consecutive marks by
setting bit CR4.COL32CM = 1.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). In Hardware and Host modes, the LOS pin goes High when a LOS condition occurs. In
Host mode, bit PSR.LOS =1 indicates a LOS condition, and will generate an interrupt if so
programmed.
2.7.4.2
Alarm Indication Signal Detection (AIS)
This function is only available in Host mode. The receiver detects an AIS pattern when it receives
fewer than three 0s in any string of 2048 bits. The device clears the AIS condition when it receives
three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
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Datasheet
ETC [ ETC ]
