LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Both Hardware and Host Modes allow QRSS mode. The QRSS pattern is normally locked to
TCLK, however, if there is no TCLK, MCLK is the clock source. Bellcore Pub 62411 defines the
T1 QRSS transmit format and ITU G.703 defines the E1 format.
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on the INSLER pin. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is “jammed”. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
A Low-to-High transition on the INSBPV pin will insert a bipolar violation in the QRSS pattern.
Note that the BPV insertion occurs regardless of whether the device is in Bipolar or Unipolar
operating mode.
In Hardware mode, connecting the TAOS pin to Midrange enables QRSS transmission. In Host
mode, setting bits CR2.EPAT0 = 0 and CR2.EPAT1=1 enables QRSS.
Figure 11. QRSS Mode
Selecting QRSS mode also enables QRSS Pattern Detection (QPD) in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. After achieving
synchronization the device drives the QPD pin Low. In the QRSS mode, any subsequent bit error in
the QRSS pattern causes QPD to go High for half an RCLK clock cycle. Note that in Host mode,
the precise relationship between QPD and RCLK depends on the CLKE pin. When CLKE is Low,
QPD goes High while RCLK is High; when CLKE is High, QPD goes High while RCLK is Low.
The edge of QPD can serve as a trigger for an external bit-error counter. A LOS condition or a loss
of QRSS synchronization will cause QPD to go High continuously. In this case, and with either
Unipolar mode or the encoders/decoders enabled, the BPV pin indicates BPVs, CODEVs or
ZEROVs.
Host mode can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. This interrupt is enabled when bit ICR.CQRSS = 0. If the QPD signal is
used to trigger a bit error counter, the interrupt could be used to start or reset the error counter.
The PSR.QRSS bit provides an indication of QRSS pattern synchronization. This bit goes to 0
when the QRSS pattern is not detected (i.e., when there are more than four errors in 128 bits). The
TQRSS bit in the Transition Status Register indicates that QRSS status has changed since the last
QRSS Interrupt Clear command.
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Datasheet
ETC [ ETC ]
