LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 4. CLKE Pin Settings1
CLKE
Pin
Valid Clock
Edge
Output
RPOS
RNEG
RDATA
SDO
Rising RCLK
Falling SCLK
Falling RCLK
Rising SCLK
Low
RPOS
RNEG
RDATA
SDO
High
1. The clock edge selection feature is not available in Hardware
mode.
Figure 4. Serial Port Data Structure
CS
SCLK
Address / Command Byte
Input (Write) Data Byte
A7
(don’t
care)
R/W
A1
A2
A3
A4
A5
A6
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
SDI
High Impedance
SDO
R/W = 1: Read operation
R/W = 0: Write operation (SDO remains high impedance)
Output (Read) Data Byte
18
Datasheet