T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store overflow or
underflow, respectively. Note that these are “sticky bits”, that is, once set to 1, they remain set until
the host reads the register. An ES overflow or underflow condition will generate a maskable
interrupt.
2.5
2.6
Hardware Mode
The LXT350 operates in Hardware mode when the MODE pin is set to Low or Midrange. In
Hardware mode individual pins are used to access and control the transceiver. In Hardware mode,
RPOS/RNEG or RDATA are valid on the rising edge of RCLK.
Note: Some functions, such as interrupt (INT), clock edge selection (CLKE), and various
diagnostic modes, are provided only in Host mode.
Host Mode
The LXT350 operates in Host mode when the MODE pin is set High. In Host mode a
microprocessor controls the LXT350 and reads its status via the serial port which provides access
to the LXT350’s internal registers.
The host microprocessor can completely configure the device, as well as get a full diagnostic/status
report, via the serial port. However, in Unipolar mode, bipolar violation (BPV) insertions and logic
error insertions are controlled by the BPV and INSLER pins, respectively. Similarly, the recovered
clock, data, and BPV detection are available only at output pins. All other mode settings and
diagnostic information are available via the serial port. See “Register Definitions” on page 28 for
details.
Figure 4 shows the serial port data structure. The registers are accessible through a 16-bit word
composed of an 8-bit Command/Address byte (bits R/W and A1-A7) and a subsequent 8-bit data
byte (bits D0-7). The R/W bit commands a read or a write operation, i.e., the direction of the
following byte. Bits A1 through A6, of the command/address byte, point to a specific register. Note
that the LXT350 address decoder ignores bits A0 and A7. Refer to Table 32 on page 45 for timing
specifications.
Host mode also allows control of data output timing. The CLKE pin determines when SDO is
valid, relative to the Serial Clock (SCLK) as shown in Table 4.
2.6.1
Interrupt Handling
In Host mode, the LXT350 provides a latched interrupt output pin (INT). When enabled, a change
in any of the Performance Status Register bits will generate an interrupt. An interrupt can also be
generated when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an
interrupt occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has
internal pull-down only. Therefore, each device that shares the INT line requires an external
pull-up resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
Datasheet
17
ETC [ ETC ]
