LXT350 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
2.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line (RTIP/RING). Recovered data is
output at RPOS/RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK.
Refer to Table 30 on page 44 for receiver timing specifications.
2.3.1
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See “Test Specifications” on page 38 for details.
2.3.2
Receive Digital Data Interface
Recovered data is routed to the Loss of Signal (LOS) Monitor. In Host mode, it also goes through
the Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled
or disabled in the receive data path or the transmit path. Received data may be routed to either the
B8ZS or HDB3 decoder or neither. Finally, the device may send the digital data to the framer as
either unipolar or bipolar data.
When decoding unipolar data to the framer, the LXT350 reports reception of bipolar violations by
driving the BPV pin High. During E1 operation in Host mode, the device can be programmed to
report HDB3 code violations and Zero Substitution Violations on the BPV pin. See “Diagnostic
Mode Operation” on page 19 for details.
2.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides the jitter attenuation function.
The JAL requires no special circuitry, such as an external quartz crystal or high-frequency clock
(higher than the line rate). Rather, its timing reference is MCLK.
In Hardware mode, the ES is a 32 x 2-bit register. Setting the JASEL pin High places the JA
circuitry in the receive data path; setting JASEL Low places the JA in the transmit data path;
setting it to Midrange disables the JA.
In Host mode, bit CR1.JASEL0 enables or disables the JA circuit while bit CR1.JASEL1 controls
the JA circuit placement as specified in Table 9 on page 29. The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 12).
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/ of a bit period. The ES produces an average
8
delay of 16 bits in the data path. An average delay of 32 bits occurs when the 64-bit ES option
selected (Host mode only). In the event of a LOS condition, with the Jitter Attenuator in the receive
path, RCLK will be derived from MCLK.
16
Datasheet
ETC [ ETC ]
