HT1621
V A L ID D A T A
t
f
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
t
r
V
t
C
L K
D D
D B
5 0 %
t
su
t
h
5 0 %
V
V
D D
G N D
D D
t
C
G N D
W R , R D
C lo c k
L K
G N D
Figure 1
t
C
S
Figure 2
V
D D
C S
5 0 %
t
su
1
t
h
1
G N D
V
D D
W R , R D
C lo c k
5 0 %
F IR S T
C lo c k
L A S T
C lo c k
G N D
Figure 3
Functional Description
Display memory
-
RAM
The static display memory (RAM) is organized
into 32´4 bits and stores the displayed data.
The contents of the RAM are directly mapped to
the contents of the LCD driver. Data in the
RAM can be accessed by the READ, WRITE,
and READ-MODIFY-WRITE commands. The
following is a mapping from the RAM to the
LCD pattern:
C O M 3
S E G 0
S E G 1
S E G 2
S E G 3
3
2
A d d r e s s 6 b its
(A 5 , A 4 , ..., A 0 )
1
C O M 2
C O M 1
C O M 0
0
System oscillator
The HT1621 system clock is used to generate
the time base/Watchdog Timer (WDT) clock fre-
quency, LCD driving clock, and tone frequency.
The source of the clock may be from an on-chip
RC oscillator (256kHz), a crystal oscillator
(32.768kHz), or an external 256kHz clock by
the S/W setting. The configuration of the sys-
tem oscillator is as shown. After the SYS DIS
command is executed, the system clock will
stop and the LCD bias generator will turn off.
That command is, however, available only for
the on-chip RC oscillator or for the crystal oscil-
lator. Once the system clock stops, the LCD dis-
play will become blank, and the time base/WDT
lose its function as well.
The LCD OFF command is used to turn the
LCD bias generator off. After the LCD bias gen-
erator switches off by issuing the LCD OFF
command, using the SYS DIS command re-
duces power consumption, serving as a system
power down command. But if the external clock
source is chosen as the system clock, using the
SYS DIS command can neither turn the oscilla-
tor off nor carry out the power down mode. The
crystal oscillator option can be applied to con-
nect an external frequency source of 32kHz to
the OSCI pin. In this case, the system fails to
9
January 10, 2001
S E G 3 1
D
3
D
2
D
1
D
0
3 1
A d d r
D a ta
D a ta 4 b its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
ETC [ ETC ]
