Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
16 Microprocessor Interface Functional Description (continued)
16.1 Introduction
The Supermapper microprocessor interface consists of a 20-bit address and a 16-bit data bus. In addition, this
block contains global control and status registers. These registers include the summary of interrupt status of major
functional blocks and the control to enable them or power them down.
16.2 Features
■ 20-bit address/16-bit data bus microprocessor interface.
■ Synchronous (16 MHz to 60 MHz)/asynchronous microprocessor interface modes.
■ Microprocessor data bus parity monitoring.
■ Summary of interrupts from major functional blocks/maskable.
■ Separate device interrupt outputs for automatic protection switch and the Supermapper global interrupt.
■ Global configuration of network performance monitoring counters operation.
■ Global software resets.
■ Global enabling and powering down of major functional blocks.
■ Miscellaneous global configuration and control.
16.3 Microprocessor Interface
This device is equipped with a generic 20-bit address/16-bit data microprocessor interface that allows operation
with most commercially available microprocessors. Device input pin MPMODE (pin AD17) is used to configure this
interface into one of two possible modes (synchronous or asynchronous). In synchronous mode (MPMODE = 1),
the microprocessor interface can operate at speeds from 16 MHz up to 60 MHz. In asynchronous mode
(MPMODE = 0), a 16 MHz to 60 MHz clock is required on the MPCLK (pin AE17) pin for proper operation.
Two parity detectors are provided for the microprocessor data bus, one for the higher-order byte and one for the
lower-order byte. The parity sense is programmed as even or odd with register bit SMPR_PARITY_EVEN_ODD
(Table 77 on page 70). The composite status of both parity detectors is indicated in register bit SMPR_PARITY_IS
(Table 73 on page 66). The interrupt from this status indicator may be masked with register bit SMPR_PARITY_IM
(Table 74 on page 67). A bad parity event does not inhibit a data transfer. The microprocessor interface is fully
functional without parity supplied by the host processor.
The interrupt status from each of the major blocks, the automatic protection switch, and the microprocessor data
bus parity are summarized in Table 73 on page 66. Each interrupt is maskable with the complementary bit set in
the interrupt mask register; see Table 74 on page 67.
Agere Systems Inc.
361
ETC [ ETC ]
