TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
13 Cross Connect (XC) Registers
Table of Contents
Contents
Page
13 Cross Connect (XC) Registers ........................................................................................................................326
13.1 Cross Connect Register Descriptions ......................................................................................................327
13.2 Cross Connect Register Map ...................................................................................................................333
Tables
Page
Table 460. XC_ID_R, XC Global Register 1 (RO) .................................................................................................327
Table 461. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W) ..................................................327
Table 462. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W) ..................................................327
Table 463. XC_PIND_SRC[1—15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W)............328
Table 464. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W)........................328
Table 465. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W)...................................................328
Table 466. XC_VT_SRC[1—14], XC1 VT Mapper Source Configuration (R/W) ...................................................329
Table 467. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configuration (R/W) ..............................329
Table 468. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configuration (R/W) .......................329
Table 469. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W).............329
Table 470. XC_TPM_SRC[1—4], XC1 Test-Pattern Monitor Source Configuration (R/W)....................................330
Table 471. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)..........................330
Table 472. XC2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W)...........................................330
Table 473. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W) ...........................................330
Table 474. XC_MISC, XC Global Register 2 (R/W)...............................................................................................330
Table 475. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W) ...........................................331
Table 476. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W) ..................................................................332
Table 477. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)...............................332
Table 478. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)...............332
Table 479. Register Address Map .........................................................................................................................333
326
Agere Systems Inc.
ETC [ ETC ]
