RTL8201N
Datasheet
Name
Description
TA
Turnaround. This is a 2-bit time-spacing between the register address and the data field of a frame to avoid
contention during a read transaction. For a read transaction, both the STA and the PHY remain in a high-
impedance state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit
time of the turnaround of a read transaction.
DATA
IDLE
Data. These are the 16 bits of data.
Idle Condition. Not truly part of the management frame. This is a high impedance state. Electrically, the
PHY’s pull-up resistor will pull the MDIO line to a logical ‘1’.
8.2. Auto-Negotiation and Parallel Detection
The RTL8201N supports IEEE 802.3u clause 28 Auto-negotiation for operation with other transceivers
supporting auto-negotiation. The RTL8201N can auto-detect the link partner’s abilities and determine the
highest speed/duplex configuration possible between the two devices. If the link partner does not support
auto-negotiation, then the RTL8201N will enable half duplex mode and enter parallel detection mode.
The RTL8201N will default to transmitting FLP (Fast Link Pulse) and wait for the link partner to
respond. If the RTL8201N receives a FLP, then the auto-negotiation process will go on. If it receives
NLP (Normal Link Pulse), then the RTL8201N will change to 10Mbps and half duplex mode. If it
receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode.
To enable auto-negotiation mode operation on the RTL8201N, pull the ANE (Auto-Negotiation Enable)
pin high. The SPEED and DUPLEX pins will set the ability content of the auto-negotiation register.
Auto-negotiation mode can be externally disabled by pulling the ANE pin low. In this case, the SPEED
pin and DUPLEX pin will change the media configuration of the RTL8201N.
The following is a list of all configurations of the ANE/SPEED/DUPLEX pins and their operation in
Fiber or UTP mode.
8.2.1. Setting the Medium Type and Interface Mode to MAC
Table 23. Setting the Medium Type and Interface Mode to MAC
FX (Pin 35)
MII/SNIB (Pin 46) Operation Mode
L
L
H
H
L
UTP mode and MII interface.
UTP mode and SNI interface.
Fiber mode and MII interface.
X
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
18
Rev. 1.2
ETC [ ETC ]
