RTL8201N
Datasheet
Address
17:10
17:9
Name
Reserved
LB
Description
Mode
Default
-
-
-
Set to 1 to enable DSP Loopback.
RW
RW
RW
RW
RW
RW
0
1
1
1
0
0
17:8
F_Link_10
F_Link_100
JBEN
Used to logic force good link in 10Mbps for diagnostic purposes.
Used to logic force good link in 100Mbps for diagnostic purposes.
Set to 1 to enable Jabber Function in 10Base-T.
Assertion of this bit causes a code error detection to be reported.
17:7
17:6
17:5
CODE_err
PME_err
17:4
Assertion of this bit causes a pre-mature end error detection to be
reported.
17:3
17:2
LINK_err
PKT_err
Assertion of this bit causes a link error detection to be reported.
RW
RW
0
0
Assertion of this bit causes a ‘detection of packet errors due to
722 ms time-out’ to be reported.
17:1
17:0
FXMODE
This bit indicates whether Fiber Mode is Enabled.
RW
RW
0
0
SNIBMODE This bit indicates whether SNI mode is Enabled.
7.10. Register 18 RX_ER Counter (REC)
Table 19. Register 18 RX_ER Counter (REC)
Address
Name
Description
Mode
Default
18:15~0
RXERCNT
This 16-bit counter increments by 1 for each invalid packet
received. The value is valid while the link is established.
RO
H’[0000]
7.11. Register 19 SNR Display Register
Table 20. Register 19 SNR Display Register
Address
Name
Description
Mode
Default
19:15~4
Reserved
Realtek Test Mode Internal use. Do not change this field without
Realtek’s approval.
-
-
19:3~0
SNR
These 4-bits show the Signal to Noise Ratio value.
RW
0000
7.12. Register 25 Test Register
Table 21. Register 25 Test Register
Description
Reserved for internal testing.
Address
25:15~12
25:11~7
Name
Mode
RW
Default
-
Test
PHYAD[4:0] Reflects the PHY address defined by external PHY address
configuration pins.
RO
00001
25:6~2
25:1
Test
Reserved for internal testing.
RO
RO
LINK10
1: 10Base-T link established
0
0
0: No 10Base-T link established
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
25:0
LINK100
RO
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
15
Rev. 1.2
ETC [ ETC ]
