RTL8201N
Datasheet
Name
RXER/
Type
Pin No.
Description
LI/O
35
Receive Error.
CONFIG[8]
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible to
use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
MDC
I
30
31
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous to
the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz.
Use an internal weak pull high resistor to prevent the bus floating.
MDIO
IO
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
6.2. RMII Interface
Table 2. RMII Interface
Name
REFCLK
CRSDV
RXD[1:0]
TXEN
Type
Pin No.
24
Description
I
O
O
I
Synchronous clock reference for receive, transmit and control interface
16
Carrier Sense/Receive Data Valid
Receive Data
19, 17
29
Transmit Enable
TXD[1:0]
RXER
I
26, 25
35
Transmit Data
O
Receive Error
6.3. SNI (Serial Network Interface) 10Mbps Only
Table 3. SNI (Serial Network Interface) 10Mbps Only
Name
COL
Type
O
Pin No.
46
Description
Collision Detect.
RXD0
CRS
O
17
Received Serial Data.
Carrier Sense.
O
47
RXC
O
22
Receive Clock.
Resolved from received data.
Transmit Serial Data.
Transmit Clock.
TXD0
TXC
I
25
24
O
Generated by PHY.
Transmit Enable.
TXEN
I
29
For MAC to indicate transmit operation.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
6
Rev. 1.2
ETC [ ETC ]
