RTL8201N
Datasheet
6. Pin Descriptions
LI: Latched Input during Power up or Reset
IO: Bi-directional input and output
O: Output
P: Power
I: Input
6.1. MII Interface
Table 1. MII Interface
Description
Transmit Clock.
Name
Type
Pin No.
TXC
O
24
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
TXEN
TXD[3:0]
RXC
I
I
29
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0]. An
internal weak pull low resistor to prevent the bus floating.
28, 27, 26, 25 Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted. An internal weak pull high resistor prevents the bus floating.
O
22
46
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
COL/
LI/O
Collision Detect.
CONFIG[6]
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode
1: SNI mode
This pin can be directly connected to GND or VCC.
CRS/
CONFIG[5]
LI/O
LI/O
47
16
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
During power on reset, this pin set high to put the RTL8201N into repeater
mode. This pin can be directly connected to GND or VCC.
RXDV/
RMII
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode
1: RMII mode
This pin can be directly connected to GND or VCC.
RXD[3:0]
O
21, 20, 19, 17 Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
5
Rev. 1.2
ETC [ ETC ]
