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NRF24L01 参数 Datasheet PDF下载

NRF24L01图片预览
型号: NRF24L01
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片的2.4 GHz收发器 [Single chip 2.4 GHz Transceiver]
分类和应用:
文件页数/大小: 38 页 / 463 K
品牌: ETC [ ETC ]
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PRELIMINARY PRODUCT SPECIFICATION  
nRF24L01 Single Chip 2.4 GHz Radio Transceiver  
Address  
(Hex)  
Mnemonic  
Bit  
Reset  
Value  
Type Description  
‘0000’ – Wait 250+86uS  
‘0001’ – Wait 500+86uS  
‘0010’ – Wait 750+86uS  
……..  
‘1111’ – Wait 4000+86uS  
(Delay defined from end of transmission  
to start of next transmission)  
ARC  
3:0  
0011  
R/W Auto Retransmit Count  
‘0000’ –Re-Transmit disabled  
‘0001’ – Up to 1 Re-Transmit  
on fail of AA  
……  
‘1111’ – Up to 15 Re-Transmit  
on fail of AA  
05  
06  
RF_CH  
Reserved  
RF_CH  
RF Channel  
R/W Only '0' allowed  
R/W Sets the frequency channel nRF24L01  
operates on  
7
6:0  
0
0000010  
RF_SETUP  
Reserved  
PLL_LOCK  
RF_DR  
RF Setup Register  
R/W Only '000' allowed  
R/W Force PLL lock signal  
R/W Data Rate  
7:5  
4
3
000  
0
1
‘0’ – 1 Mbps  
‘1’ – 2 Mbps  
RF_PWR  
2:1  
0
11  
1
R/W Set RF output power in TX mode  
'00' – -18 dBm  
'01' – -12 dBm  
'10' – -6 dBm  
'11' – 0 dBm  
LNA_HCURR  
STATUS  
R/W Setup LNA gain  
07  
Status Register (In parallel to the SPI  
instruction word applied on the MOSI  
pin, the STATUS register is shifted  
serially out on the MISO pin)  
Reserved  
RX_DR  
7
6
0
0
R/W Only '0' allowed  
R/W Data Ready RX FIFO interrupt. Set high  
when new data arrives RX FIFO13.  
Write 1 to clear bit.  
TX_DS  
5
0
R/W Data Sent TX FIFO interrupt. Set high  
when packet sent on TX. If AUTO_ACK  
is activated, this bit will be set high only  
when ACK is received.  
Write 1 to clear bit.  
MAX_RT  
RX_P_NO  
4
0
R/W Maximum number of TX retries interrupt  
Write 1 to clear bit. If MAX_RT is  
set it must be cleared to enable  
further communication.  
3:1  
111  
R
Data pipe number for the payload  
available for reading from RX_FIFO  
000-101: Data Pipe Number  
110: Not Used  
111: RX FIFO Empty  
TX_FULL  
0
0
R
TX FIFO full flag. 1: TX FIFO full. 0:  
13 The Data Ready interrupt is set by a new packet arrival event. The procedure for handling this  
interrupt should be: 1) read payload via SPI, 2) clear RX_DR interrupt, 3) read FIFO_STATUS to  
check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat  
from 1).  
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway  
Revision: 1.1  
-
Phone +4772898900  
-
Fax +4772898989  
November 2005  
Page 22 of 38  
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