PRELIMINARY PRODUCT SPECIFICATION
nRF24L01 Single Chip 2.4 GHz Radio Transceiver
Address
(Hex)
Mnemonic
Bit
Reset
Value
Type Description
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
14
15
16
17
RX_PW_P3
Reserved
RX_PW_P3
7:6
5:0
00
0
R/W Only '00' allowed
R/W Number of bytes in RX payload in data
pipe 3 (1 to 32 bytes).
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
RX_PW_P4
Reserved
RX_PW_P4
7:6
5:0
00
0
R/W Only '00' allowed
R/W Number of bytes in RX payload in data
pipe 4 (1 to 32 bytes).
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
RX_PW_P5
Reserved
RX_PW_P5
7:6
5:0
00
0
R/W Only '00' allowed
R/W Number of bytes in RX payload in data
pipe 5 (1 to 32 bytes).
0 Not Legal
1 = 1 byte
…
32 = 32 bytes
FIFO_STATUS
Reserved
TX_REUSE
FIFO Status Register
R/W Only '0' allowed
7
6
0
0
R
Reuse last sent data packet if set high.
The packet will be repeatedly resent as
long as CE is high.
TX_REUSE is set by the SPI instruction
REUSE_TX_PL, and is reset by the SPI
instructions W_TX_PAYLOAD or
FLUSH TX
TX_FULL
5
4
0
1
R
R
TX FIFO full flag. 1: TX FIFO full. 0:
Available locations in TX FIFO.
TX FIFO empty flag. 1: TX FIFO empty.
0: Data in TX FIFO.
TX_EMPTY
Reserved
RX_FULL
3:2
1
00
0
R/W Only '00' allowed
R
RX FIFO full flag. 1: RX FIFO full. 0:
Available locations in RX FIFO.
RX FIFO full flag. 1: RX FIFO empty. 0:
Data in RX FIFO.
Written by separate SPI command TX
data payload register 1 - 32 bytes.
This register is implemented as a FIFO
with 3 levels.
RX_EMPTY
TX_PLD
0
1
R
N/A
N/A
255:0
X
W
Used in TX mode only
RX_PLD
255:0
X
R
Written by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO
with 3 levels.
All receive channels share the same FIFO
Table 11 Memory map of nRF24L01
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway
Revision: 1.1
-
Phone +4772898900
-
Fax +4772898989
November 2005
Page 24 of 38
ETC [ ETC ]
