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ILI9325 参数 Datasheet PDF下载

ILI9325图片预览
型号: ILI9325
PDF下载: 下载PDF文件 查看货源
内容描述: 的a-Si TFT LCD单芯片驱动器240RGBx320分辨率和26万色 [a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color]
分类和应用: 驱动器
文件页数/大小: 111 页 / 1190 K
品牌: ETC [ ETC ]
 浏览型号ILI9325的Datasheet PDF文件第39页浏览型号ILI9325的Datasheet PDF文件第40页浏览型号ILI9325的Datasheet PDF文件第41页浏览型号ILI9325的Datasheet PDF文件第42页浏览型号ILI9325的Datasheet PDF文件第44页浏览型号ILI9325的Datasheet PDF文件第45页浏览型号ILI9325的Datasheet PDF文件第46页浏览型号ILI9325的Datasheet PDF文件第47页  
a-Si TFT LCD Single Chip Driver  
240RGBx320 Resolution and 262K color  
ILI9325  
7.5.4. 6-bit RGB Interface  
The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. The display operation is synchronized  
with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in  
synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable  
signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system  
interface (i80/SPI).  
RGB interface with 6-bit data bus  
1st Transfer  
2nd Transfer  
3rd Transfer  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
Input Data  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
RGB Assignment  
Data transfer synchronization in 6-bit RGB interface mode  
ILI9325 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode.  
The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a  
mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at  
the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the  
next frame. This function is expedient for moving picture display, which requires consecutive data transfer in  
light of minimizing effects from failed data transfer and enabling the system to return to a normal state.  
Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK).  
Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data  
transfer correctly. Otherwise it will affect the display of that frame as well as the next frame.  
HSYNC  
ENABLE  
DOTCLK  
1st 2nd 3rd  
DB[17:12]  
1st 2nd 3rd 1st 2nd 3rd  
1st 2nd 3rd  
Transfer synchronization  
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,  
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.  
Page 43 of 111  
Version: 0.35  
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