Data Sheet
June 1999
ORCA Series 2 FPGAs
Pin Information (continued)
Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA
Pinout
Pin
2C/2T10A Pad 2C/2T12A Pad 2C/2T15A/B Pad 2C/2T26A Pad OR2T40A/B Pad
Function
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
F2
G4
F3
F1
G2
G1
G3
H2
J4
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8A
PL9D
PL9A
PL10D
PL10A
PL11D
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL1D
PL1A
I/O
I/O
PL2D
PL2A
I/O
I/O
PL3D
PL3A
I/O-A0
I/O
PL4D
PL4B
I/O
I/O
PL2A
PL3D
—
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL4A
I/O
VDD5
I/O-VDD5
I/O
PL5C
PL5B
PL3C
—
I/O
PL6D
PL7D
PL7C
PL7B
I/O
PL3B
—
I/O
I/O
—
I/O
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL8D
PL9D
PL9C
PL9B
I/O-A1
I/O
I/O
H1
H3
J2
I/O
PL9A
I/O-A2
I/O
PL10D
PL10C
PL10B
PL10A
PL11D
PL11A
PL12D
PL12A
PL13D
PL13A
PL14D
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
J1
I/O
K2
J3
I/O
I/O-A3
I/O
K1
K4
L2
I/O
I/O
K3
L1
I/O-A4
I/O-A5
I/O
M2
M1
L3
I/O
I/O-A6
I/O
N2
M4
N1
M3
P2
I/O
I/O
I/O-A7
I/O
Notes:
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane
of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
106
Lucent Technologies Inc.
ETC [ ETC ]
