Data Sheet
June 1999
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
Function
2C/2T06A Pad
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
2C/2T08A Pad
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
2C/2T10A Pad
PR15B
PR15C
PR15D
PR14A
PR14C
PR14D
PR13A
PR13B
PR13C
PR12A
PR12B
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
2C/2T12A Pad
PR17B
PR17C
PR17D
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
2C/2T15A/B Pad
PR18A
PR18B
PR18D
PR17A
PR17D
PR16A
PR16C
PR16D
PR15A
PR15D
PR14A
PR13A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
U20
T18
T19
T20
R18
P17
R19
R20
P18
P19
P20
N18
N19
N20
M17
M18
M19
M20
L19
L18
L20
K20
K19
K18
K17
J20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O-VDD5
I/O
I/O-M2
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
PR9B
PR9C
PR9D
PR8A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PR8B
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR8C
PR8D
PR7A
PR7B
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR5B
PR5D
PR4A
PR7C
PR7D
PR6A
J19
J18
J17
I/O-VDD5
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O-RD
PR6B
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR6B
PR6D
PR5A
H20
H19
H18
G20
G19
F20
G18
F19
E20
G17
F18
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4B
PR4C
PR4D
PR3A
PR4C
PR4D
PR3A
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
Lucent Technologies Inc.
95
ETC [ ETC ]
