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OR2C10A-2BA240I 参数 Datasheet PDF下载

OR2C10A-2BA240I图片预览
型号: OR2C10A-2BA240I
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列 [Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列
文件页数/大小: 192 页 / 2992 K
品牌: ETC [ ETC ]
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Data Sheet  
June 1999  
ORCA Series 2 FPGAs  
Pin Information (continued)  
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B  
256-Pin PBGA Pinout  
Pin  
Function  
2C/2T06A Pad  
PL1D  
PL1C  
PL1B  
PL1A  
2C/2T08A Pad  
PL1D  
PL1B  
PL1A  
PL2D  
PL2C  
PL2B  
PL2A  
PL3D  
PL3C  
PL3B  
PL3A  
2C/2T10A Pad  
PL1D  
PL1B  
PL1A  
PL2D  
PL2C  
PL2B  
PL2A  
PL3D  
PL3C  
PL3B  
PL3A  
PL4D  
PL4A  
PL5C  
PL5B  
PL5A  
PL6D  
PL6C  
PL6B  
PL6A  
PL7D  
PL7C  
PL7B  
PL7A  
PL8D  
PL8C  
PL8B  
PL8A  
PL9D  
PL9C  
PL9B  
PL9A  
PL10D  
PL10C  
PL10B  
PL10A  
PL11D  
PL11C  
PL11B  
PL11A  
2C/2T12A Pad  
PL1D  
PL1C  
PL1B  
2C/2T15A/B Pad  
PL1D  
C2  
D2  
D3  
E4  
C1  
D1  
E3  
E2  
E1  
F3  
G4  
F2  
F1  
G3  
G2  
G1  
H3  
H2  
H1  
J4  
J3  
J2  
J1  
K2  
K3  
K1  
L1  
L2  
L3  
I/O  
I/O  
I/O  
I/O-A0  
I/O  
I/O  
I/O  
I/O-VDD5  
I/O  
I/O  
I/O-A1  
I/O  
I/O-A2  
I/O  
I/O  
I/O-A3  
I/O  
I/O  
PL1C  
PL1B  
PL2D  
PL2A  
PL3D  
PL3A  
PL4D  
PL4A  
PL5D  
PL5A  
PL6D  
PL6A  
PL7D  
PL7B  
PL7A  
PL8D  
PL8C  
PL8B  
PL8A  
PL9D  
PL9C  
PL9B  
PL9A  
PL10D  
PL10C  
PL10B  
PL10A  
PL11D  
PL11C  
PL11B  
PL11A  
PL12D  
PL12C  
PL12B  
PL12A  
PL13D  
PL13C  
PL13B  
PL13A  
PL2D  
PL2C  
PL2B  
PL2A  
PL3D  
PL3A  
PL4D  
PL4A  
PL5D  
PL5A  
PL6D  
PL6B  
PL6A  
PL2D  
PL2C  
PL2B  
PL2A  
PL3D  
PL3C  
PL3B  
PL3A  
PL4D  
PL4C  
PL4B  
PL4A  
PL5D  
PL5C  
PL5B  
PL5A  
PL6D  
PL6C  
PL6B  
PL6A  
PL7D  
PL7C  
PL7B  
PL7A  
PL8D  
PL8C  
PL8B  
PL8A  
PL9D  
PL9C  
PL9B  
PL9A  
PL4D  
PL4C  
PL4B  
PL4A  
PL5D  
PL5C  
PL5B  
PL5A  
PL6D  
PL6C  
PL6B  
PL6A  
PL7D  
PL7C  
PL7B  
PL7A  
PL8D  
PL8C  
PL8B  
PL8A  
PL9D  
PL9C  
PL9B  
PL9A  
PL10D  
PL10C  
PL10B  
PL10A  
PL7D  
PL7C  
PL7B  
I/O  
PL7A  
I/O-A4  
I/O-A5  
I/O  
I/O  
I/O-A6  
I/O  
I/O  
I/O  
I/O-A7  
I/O  
I/O-VDD5  
I/O  
I/O-A8  
I/O-A9  
I/O  
I/O  
I/O-A10  
I/O  
I/O  
I/O  
I/O-A11  
PL8D  
PL8C  
PL8B  
PL8A  
PL9D  
PL9C  
PL9B  
PL9A  
PL10D  
PL10C  
PL10B  
PL10A  
PL11D  
PL11C  
PL11B  
PL11A  
PL12D  
PL12C  
PL12B  
PL12A  
L4  
M1  
M2  
M3  
M4  
N1  
N2  
N3  
P1  
P2  
R1  
Notes:  
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.  
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.  
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.  
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground  
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.  
92  
Lucent Technologies Inc.  
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