Data Sheet
June 1999
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.
Speed
Parameter
Symbol
Unit
-2
-3
-4
-5
-6
-7
Min Max Min Max Min Max Min Max Min Max Min Max
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
TRC
MEM*_ADEL
5.1
—
—
4.0
3.6
—
—
2.8
2.7
—
—
2.1
2.4
—
—
1.7
2.3
—
—
1.4
2.0
—
—
1.3 ns
ns
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK) MEM*_ASET 2.4
Clock to PFU Out (CK to Q[3:0])—Register REG_DEL
—
2.4
1.8
—
—
2.0
1.2
—
—
1.9
1.1
—
—
1.5
1.0
—
—
1.3
1.0
—
—
1.0 ns
ns
—
Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.
Speed
Parameter
Symbol
Unit
-7
-8
Min
Max
Min
Max
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
TRC
MEM*_ADEL
1.9
—
—
1.3
1.8
—
—
1.0
ns
ns
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
MEM*_ASET
REG_DEL
0.9
—
—
1.0
0.8
—
—
1.0
ns
ns
TRC
A[3:0], B[3:0]
F[3:0]
MEM*_ADEL
5-3226(F).r4
Figure 55. Read Operation—Flip-Flop Bypass
A[3:0], B[3:0]
MEM*_ASET
CK
REG_DEL
Q[3:0]
5-3227(F).r4
Figure 56. Read Operation—LUT Memory Loading Flip-Flops
138
Lucent Technologies Inc.
ETC [ ETC ]
