Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Function
Input Buffer with failsafe
Block type
FIA2
Path
→
t 1
T
Block type
IN
OUT
MIN.
0.176
0.138
0.176
0.138
1.184
2.208
1.184
2.208
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
Function
Normal
Schmitt
Clock
no resistor
FIA2
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
0.266
0.198
0.266
0.198
1.976
3.267
1.976
3.267
0.417
0.328
0.417
0.328
4.048
5.483
4.048
5.483
0.011
0.007
0.011
0.007
0.008
0.012
0.008
0.012
0.016
0.009
0.016
0.009
0.011
0.015
0.011
0.015
0.022
0.012
0.022
0.012
0.017
0.022
0.017
0.022
A
A
A
A
→
→
→
→
Y
Y
Y
Y
FDA2
1
1
3
6
FDA2
FIE2W
FDE2W
FIE2W
FDE2W
Logic Diagram for "Normal"
Truth Table
A
Y
A
H01
N01
Y
1
0
1
0
Logic Diagram for "Schmitt"
Input
Output
Block type
FIA2 to FDA2
Symbol Fan-In Symbol Fan-Out
A
-
Y
34
A
H01
N01
Y
FIE2W to FDE2W
A
-
Y
37
Logic Diagram for "Clock"
Block Library A13872EJ5V0BL
1 - 66
Block Library A13872EJ5V0BL
1 - 67
ETC [ ETC ]
