Chapter 1 Interface Block
Chapter 1 Interface Block
Switching speed
t LD0 (ns)
5.0 V
Function
Input Buffer
Block type
FI02
Path
→
t 1
T
Block type
IN
OUT
MIN.
0.176
0.138
0.176
0.138
0.176
0.138
0.176
0.138
1.184
2.208
1.184
2.208
1.184
2.208
1.184
2.208
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
Function
Normal
Schmitt
Clock
no resistor
FI02
with 50 KΩ P/D
with 50 KΩ P/U
with 5 KΩ P/U
I/O cells int. Cells
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
(HH)
(LL)
0.266
0.197
0.266
0.197
0.266
0.197
0.266
0.197
1.976
3.267
1.976
3.267
1.976
3.267
1.976
3.267
0.417
0.328
0.417
0.328
0.417
0.328
0.417
0.328
4.048
5.483
4.048
5.483
4.048
5.483
4.048
5.483
0.011
0.007
0.011
0.007
0.011
0.007
0.011
0.007
0.008
0.012
0.008
0.012
0.008
0.012
0.008
0.012
0.016
0.009
0.016
0.009
0.016
0.009
0.016
0.009
0.011
0.015
0.011
0.015
0.011
0.015
0.011
0.015
0.022
0.012
0.022
0.012
0.022
0.012
0.022
0.012
0.017
0.022
0.017
0.022
0.017
0.022
0.017
0.022
A
A
A
A
A
A
A
A
→
→
→
→
→
→
→
→
Y
Y
Y
Y
Y
Y
Y
Y
FID2
FIU2
FIW2
1
1
3
6
FID2
FIS2W
FDS2W
FUS2W
FWS2W
FIU2
FIW2
Logic Diagram for "Normal"
Truth Table
FIS2W
FDS2W
FUS2W
FWS2W
A
Y
A
H01
N01
Y
1
0
1
0
Logic Diagram for "Schmitt"
Input
Output
Block type
FI02 to FIW2
Symbol Fan-In Symbol Fan-Out
A
A
-
-
Y
Y
34
37
A
H01
N01
Y
FIS2W to FWS2W
Logic Diagram for "Clock"
Block Library A13872EJ5V0BL
1 - 64
Block Library A13872EJ5V0BL
1 - 65
ETC [ ETC ]
