Chapter 2 Function Block
D-F/F with SB, 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
(HH) 0.365
(HL) 0.431
(HH) 0.582
(HL) 0.493
(LH) 0.335
0.560
0.699
0.978
0.779
0.620
0.385
1.005
1.310
1.936
1.416
1.172
0.658
1.740
1.740
1.860
0.000
0.000
0.000
0.550
0.380
2.313
1.506
1.007
1.309
1.051
1.740
1.730
1.860
0.000
0.000
0.000
0.550
0.380
1.688
1.374
1.137
0.976
0.929
1.750
1.750
1.880
0.000
0.000
0.000
0.570
0.340
1.517
1.267
0.015
0.013
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
0.021
0.018
D0
D1
C
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
34
F616S
C
C
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
→
QB
Low Power
F616S
11
F616SQ
10
F616SB
10
x1
x2
x4
SB
SB
→
→
Q
QB
(LL)
D0
D1
A
D0
D1
A
SB
SB
C
0.189
0.720
0.720
0.740
0.240
0.240
0.230
0.440
0.370
0.755
0.577
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
Logic Diagram for "Normal"
Truth Table for "Normal"
SB
D0
D1
C
SB
A
Q
QB
H04
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
1
D0 H01
D1 H02
N01
Q
0
X
X
X
X
X
Hold
1
Min Pulse
SB
(HH) 0.366
(HL) 0.429
(LH) 0.316
0.561
0.695
0.559
0.011
0.010
0.011
0.015
0.013
0.015
0.021
0.017
0.021
D0
D1
C
SB
A
1.0
1.0
1.0
2.2
1.0
Q
35
0
1
F616SQ
C
→
Q
Q
C
A
H03
H05
1
0
N02 QB
SB
→
X
X
Hold
0
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
SB
SB
C
0.720
0.720
0.730
0.240
0.240
0.230
0.440
0.370
0.603
0.535
X
1
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
SB
D0
D1
C
SB
A
Q
H04
Min Pulse
SB
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
0
1
(HH) 0.376
(HL) 0.350
0.604
0.553
0.501
0.011
0.011
0.010
0.016
0.014
0.014
0.023
0.020
0.019
D0
D1
C
SB
A
1.0
1.0
1.0
2.2
1.0
QB
32
F616SB
C
→
QB
QB
D0 H01
D1 H02
N01
Q
X
X
X
X
X
Hold
0
(LL)
D0
D1
A
D0
D1
A
SB
SB
C
0.282
0.730
0.730
0.750
0.250
0.250
0.230
0.450
0.350
0.549
0.521
SB
→
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
C
A
H03
H05
1
1
X
X
Hold
1
X
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
Min Pulse
SB
SB
D0
D1
C
SB
A
QB
H04
0
1
X
X
X
0
1
1
1
1
1
1
0
0
0
0
1
1
1
X
1
0
D0 H01
D1 H02
X
X
X
X
X
Hold
1
C
A
H03
H05
1
0
N01 QB
X
X
Hold
0
X
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 296
Block Library A13872EJ5V0BL
2 - 297
ETC [ ETC ]
