Chapter 2 Function Block
D-F/F (CB) with 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
CB
OUT
MIN.
(LH) 0.387
(LL) 0.360
(LH) 0.453
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
0.641
0.586
0.752
0.857
1.217
1.095
1.444
1.627
1.450
1.450
1.580
0.060
0.060
0.000
1.954
1.217
1.097
1.450
1.450
1.590
0.050
0.050
0.000
1.543
0.921
1.087
1.450
1.440
1.580
0.060
0.060
0.000
1.421
0.015
0.013
0.015
0.013
0.021
0.017
0.021
0.017
D0
D1
CB
A
1.0
1.0
1.0
1.0
Q
35
35
F661S
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
CB
→
QB
Low Power
(LL)
D0
D1
A
D0
D1
A
0.512
0.670
0.670
0.700
0.270
0.270
0.290
0.720
F661S
10
F661SQ
9
F661SB
9
x1
x2
x4
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Logic Diagram for "Normal"
Truth Table for "Normal"
CB
D0
D1
CB
A
Q
QB
D0 H01
D1 H02
N01
Q
(LH) 0.387
0.641
0.587
0.011
0.010
0.015
0.013
0.021
0.017
D0
D1
CB
A
1.0
1.0
1.0
1.0
Q
35
F661SQ
CB
→
Q
(LL)
D0
D1
A
D0
D1
A
0.359
0.670
0.670
0.700
0.270
0.270
0.290
0.595
0
1
X
X
X
0
0
0
0
1
1
1
0
1
1
0
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
CB H03
X
X
X
X
Hold
Hold
A
H04
N02 QB
0
1
1
0
1
X
CB
(LH) 0.301
0.489
0.575
0.011
0.011
0.015
0.014
0.022
0.020
D0
D1
CB
A
1.0
1.0
1.0
1.0
QB
34
F661SB
CB
→
QB
X:Irrelevant
(LL)
D0
D1
A
D0
D1
A
0.346
0.680
0.680
0.700
0.280
0.280
0.290
0.563
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Min Pulse
Logic Diagram for "Q output"
Truth Table for "Q output"
D0
D1
CB
A
Q
D0 H01
D1 H02
N01
Q
CB
0
1
X
X
X
0
0
0
0
1
1
1
0
1
CB H03
X
X
X
X
Hold
0
A
H04
1
1
X
Hold
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
D0
D1
CB
A
QB
D0 H01
D1 H02
0
1
X
X
X
0
0
0
0
1
1
1
1
0
CB H03
X
X
X
X
Hold
1
A
H04
N01 QB
1
0
X
Hold
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 300
Block Library A13872EJ5V0BL
2 - 301