Chapter 2 Function Block
D-F/F with R, 2 to 1 Selector
Chapter 2 Function Block
Switching speed
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.010
0.011
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
(HH) 0.377
(HL) 0.408
(HH) 0.498
(HL) 0.580
(HL) 0.361
(HH) 0.180
0.574
0.659
0.824
0.928
0.604
0.329
1.034
1.222
1.571
1.711
1.129
0.573
2.140
2.130
2.290
0.000
0.010
0.000
1.240
0.270
2.107
1.596
1.029
1.214
1.050
2.150
2.140
2.300
0.000
0.000
0.000
1.250
0.270
1.585
1.495
0.987
1.034
0.817
2.020
2.000
2.160
0.000
0.000
0.000
1.110
0.240
1.426
1.298
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.019
0.017
0.022
D0
D1
C
R
A
1.0
1.0
1.0
2.2
1.0
Q
35
34
F642S
C
C
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
→
QB
Low Power
F642S
11
F642SQ
10
F642SB
10
x1
x2
x4
R
R
→
→
Q
QB
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
R
R
C
R
0.730
0.730
0.730
0.280
0.280
0.260
0.410
0.400
0.795
0.582
Logic Diagram for "Normal"
Truth Table for "Normal"
D0
D1
C
R
A
Q
QB
D0 H01
D1 H02
N01
Q
0
1
X
X
X
0
0
0
0
0
0
0
1
0
0
0
1
1
1
X
0
1
1
0
C
A
H03
H05
X
X
X
X
X
Hold
1
Min Pulse
N02 QB
(HH) 0.372
(HL) 0.401
(HL) 0.337
0.570
0.653
0.564
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
D0
D1
C
R
A
1.0
1.0
1.0
2.2
1.0
Q
35
0
1
F642SQ
C
→
Q
Q
1
0
H04
R
R
→
X
X
Hold
1
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
R
R
C
R
0.740
0.740
0.740
0.270
0.280
0.260
0.410
0.400
0.577
0.533
X
0
X:Irrelevant
Logic Diagram for "Q output"
Truth Table for "Q output"
D0
D1
C
R
A
Q
D0 H01
D1 H02
N01
Q
Min Pulse
0
1
X
X
X
0
0
0
0
0
0
0
1
0
0
0
1
1
1
X
0
1
(HH) 0.329
(HL) 0.358
(HH) 0.262
0.528
0.572
0.434
0.011
0.011
0.011
0.015
0.015
0.015
0.022
0.022
0.022
D0
D1
C
R
A
1.0
1.0
1.0
2.2
1.0
QB
34
F642SB
C
→
QB
QB
C
A
H03
H05
X
X
X
X
X
Hold
0
R
→
Set up time
Set up time
Set up time
Hold time
Hold time
Hold time
Release time
Removal time
Min Pulse
D0
D1
A
D0
D1
A
R
R
C
R
0.750
0.740
0.740
0.280
0.290
0.270
0.420
0.390
0.564
0.500
1
1
H04
R
X
X
Hold
0
X
X:Irrelevant
Logic Diagram for "QB output"
Truth Table for "QB output"
Min Pulse
D0
D1
C
R
A
QB
D0 H01
D1 H02
0
1
X
X
X
0
0
0
0
0
0
0
1
0
0
0
1
1
1
X
1
0
C
A
H03
H05
X
X
X
X
X
Hold
1
N01 QB
1
0
H04
R
X
X
Hold
1
X
X:Irrelevant
Block Library A13872EJ5V0BL
2 - 288
Block Library A13872EJ5V0BL
2 - 289
ETC [ ETC ]
