Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
Conversion Time
ø = 1 MHz
62 µs
CKS
0
Conversion Period
62/ø (initial value)
31/ø
ø = 5 MHz
31 µs
1
31 µs
15.5 µs*
Note:
*
Operation is not guaranteed if the conversion time is less than 15.5 µs. Set bit 7 for a
value of at least 15.5 µs.
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
1
Disables start of A/D conversion by external trigger
(initial value)
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note:
*
The external trigger (ADTRG) edge is selected by bit INTEG4 of IEGR. See 1. IRQ
edge select register (IEGR) in 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
335
ETC [ ETC ]
