Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled*
(initial value)
1
Note:
*
TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3X pin.
The combination of CKE1 and CKE0 determines whether the SCK3X pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10-4 in 10.1.3, Operation.
Bit 1
CKE1
0
Bit 0
CKE0
0
Description
Communication Mode
Asynchronous
Synchronous
Clock Source
Internal clock
Internal clock
Internal clock
Reserved
SCK3X Pin Function
I/O port*1
Serial clock output*1
Clock output*2
0
1
1
1
0
1
Asynchronous
Synchronous
Asynchronous
Synchronous
External clock
External clock
Reserved
Clock input*3
Serial clock input
Asynchronous
Synchronous
Reserved
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
278
ETC [ ETC ]
