4. Port mode register 3 (PMR3)
PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3
pins. Only the bit relating to the watchdog timer is described here. For details of the other bits,
see section 8, I/O Ports.
Bit 5: Watchdog timer source clock select (WDCKS)
WDCKS
Description
0
1
ø/8192 selected
øw/32 selected
(initial value)
9.6.3
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (ø/8192 or
øw/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): ø/8192 is
selected when WDCKS is cleared to 0, and øw/32 when set to 1. When TCSRWE = 1 in TCSRW,
if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When
the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow,
and an internal reset signal is generated one base clock (ø or øSUB) cycle later. The internal reset
signal is output for 512 clock cycles of the øOSC clock. It is possible to write to TCW, causing
TCW to count up from the written value. The overflow period can be set in the range from 1 to
256 input clocks, depending on the value written in TCW.
238
ETC [ ETC ]
