TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: An input capture signal may be generated when TMIG is modified.
2. Input capture register GF (ICRGF)
*
7
6
5
4
3
2
1
0
Bit:
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
0
0
0
0
0
0
0
Initial value:
Read/Write:
0
R
R
R
R
R
R
R
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2øSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
3. Input capture register GR (ICRGR)
7
6
5
4
3
2
1
0
Bit:
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
0
0
0
0
0
0
0
Initial value:
Read/Write:
0
R
R
R
R
R
R
R
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2øSUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
218
ETC [ ETC ]
