Bit 2: Timer F module standby mode control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
1
Timer F is set to module standby mode
Timer F module standby mode is cleared
(initial value)
9.4.3
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time
(using two consecutive byte-size MOV instructions), and the upper byte must be accessed before
the lower byte. Data will not be transferred correctly if only the upper byte or only the lower byte
is accessed.
In 8-bit mode, there are no restrictions on the order of access.
207
ETC [ ETC ]
