4. Timer control/status register F (TCSRF)
Bit:
7
OVFH
0
6
CMFH
0
5
OVIEH
0
4
CCLRH
0
3
OVFL
0
2
CMFL
0
1
OVIEL
0
0
CCLRL
0
Initial value:
Read/Write:
*
*
*
*
R/(W)
R/(W)
R/(W)
R/W
R/W
R/(W)
R/W
R/W
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing conditions:
(initial value)
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCFH overflows from H'FF to H'00
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing conditions:
(initial value)
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches the OCRFH value
204
ETC [ ETC ]
