Table 5-4 Clock Frequency and Settling Time (times are in ms)
STS2
STS1
STS0
Waiting Time
8,192 states
16,384 states
32,768 states
65,536 states
131,072 states
2 states (not available)
8 states
2 MHz
4.1
1 MHz
8.2
0.5 MHz
16.4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.2
16.4
32.8
16.4
32.8
65.5
0.001
0.004
0.008
32.8
65.5
65.5
131.1
262.1
0.004
0.016
0.032
131.1
0.002
0.008
0.016
16 states
•
When an external clock is used
STS2 = 1, STS1 = 0 and STS0 = 1 are recommended. Other values can be set, but with other
settings, operation may start before the standby time is over.
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high-
impedance state (except pins for which the pull-up MOS is designated as on). Figure 5-2 shows
the timing in this case.
ø
Internal data bus
SLEEP instruction fetch Fetch of next instruction
SLEEP instruction execution
Port output
Internal processing
High-impedance
Pins
Active (high-speed) mode or active (medium-speed) mode
Standby mode
Figure 5-2 Standby Mode Transition and Pin States
107
ETC [ ETC ]
