Si3210/Si3211/Si3212
Register 10. Two-Wire Impedance Synthesis Control
Bit
D7
D6
D5
D4
D3
D2
D1
TISS[2:0]
R/W
D0
Name
Type
CLC[1:0]
R/W
TISE
R/W
Reset settings = 0000_1000
Bit
7:6
5:4
Name
Function
Reserved
CLC[1:0]
Read returns zero.
Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3
TISE
Two-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0
TISS[2:0]
Two-Wire Impedance Synthesis Selection.
000 = 600 Ω
001 = 900 Ω
010 = 600 Ω + 2.16 µF
011 = 900 Ω + 2.16 µF
100 = CTR21 (270 Ω + 750 Ω || 150 nF)
101 = Australia/New Zealand #1 (220 Ω + 820 Ω || 120 nF)
110 = Slovakia/Slovenia/South Africa (220 Ω + 820 Ω || 115 nF)
111 = New Zealand #2 (370 Ω + 620 Ω || 310 nF)
Preliminary Rev. 1.11
61
ETC [ ETC ]
