RTL8201BL
1) 100Base-FX Transmit Function: The 100Base-FX transmit function is performed as follows: Di-bits of TXD are
processed as 100Base-TX, except without scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in
100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in
differential-pairs form.
2) In 100Base-FX Receive Function: The 100Base-FX receive function is performed as follows: The signal is received
through PECL receiver inputs from the fiber transceiver, and directly passed to the clock recovery circuit for data/clock
recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
7.8.3 10Base Tx/Rx
1) 10Base Transmit Function: The 10Base transmit function is performed as follows: The transmit 4 bits nibbles(TXD[0:3])
clocked in 2.5MHz(TXC) is first feed to parallel to serial converter, then put the 10Mbps NRZ signal to Manchester
coding. The Manchester encoder converts the 10 Mbps NRZ data into a Manchester Encoded data stream for the TP
transmitter and adds a start of idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Then, the encoded data
stream is shaped by band- limited filter embedded in RTL8201BL and then transmitted to TP line.
2) 10Base Receive function: The 10Base receive function is performed as follows: In 10Base receive mode, The
Manchester decoder in RTL8201BL converts the Manchester encoded data stream from the TP receiver into NRZ data by
decoding the data and stripping off the SOI pulse. Then, the serial NRZ data stream is converted to parallel 4 bit nibble
signal(RXD[0:3]).
7.9 Repeater Mode Operation
Setting bit 15 of register 17 to 1 or pulling the RPTR pin high will set the RTL8201BL into repeater mode. In repeater mode,
the RTL8201BL will assert CRS high only when receiving a packet. In NIC mode, the RTL8201BL will assert CRS high both
in transmitting and receiving packets. If using the RTL8201BL in a repeater, please set the RTL8201BL to Repeater mode, and
if using the RTL8201BL in a NIC or switch application, please set the default mode. NIC/Switch mode is the default setting
and has the RPTR pin pulled low or bit 15 of register 17 is set to 0.
7.10 Reset, and Transmit Bias(RTSET)
The RTL8201BL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by
setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the registers and re-initialize them, and the media
interface will first disconnect and restart the auto-negotiation/parallel detection process.
The RTSET pin must be pulled low by a 5.9KΩ resister with 1% accuracy to establish an accurate transmit bias, this will affect
the signal quality of the transmit waveform. Keep it’s circuitry away from other clock traces or transmit/receive paths to avoid
signal interference.
7.11 3.3V power supply and voltage conversion circuit
RTL8201BL is fabricated in 0.25um process. The core circuit needs to be powered by 2.5V , however, the circuit of digital IO
and DAC need 3.3V power supply. RTL8201BL has embedded a regulator to convert 3.3V to 2.5V. Just like many commercial
voltage conversion devices, The 2.5V output pin(PWFBOUT) of this circuit requires the use of an output capacitor(22uF
tantalum capacitor) as part of the device frequency compensation and another small capacitor(0.1uF) for high frequency noise
de-coupling. And PWFBIN is fed with the 2.5V power from PWFBOUT through a ferrite bead as below figure shown.
Strongly emphasize here, could not provide external 2.5V produced by any other power device for PWFBOUT and PWFBIN.
The analog and digital Ground planes should be as large and intact as possible. If the ground plane is large enough, the analog
and digital grounds can be separated, which is a more ideal configuration. However, if the total ground plane is not sufficiently
large, partition of the ground plane is not a good idea. In this case, all the ground pins can be connected together to a larger
single and intact ground plane.
2002-03-29
Rev.1.2
19
ETC [ ETC ]
