RTL8201BL
8.2.2 MII Timing of Reception Cycle
Shown is an example of transfer of a packet from PHY to MAC in MII interface
Symbol
t1
Description
RXCLK high pulse width
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
10Mbps
100Mbps
14
140
14
20
200
20
200
40
400
26
260
26
t2
t3
t4
t5
t6
t7
t8
t9
RXCLK low pulse width
RXCLK period
10Mbps
100Mbps
140
260
10Mbps
RXER, RXDV, RXD[0:3] setup to 100Mbps
10
6
RXCLK rising edge
10Mbps
RXER, RXDV, RXD[0:3] hold after 100Mbps
10
RXCLK rising edge
10Mbps
6
ns
ns
ns
ns
ns
ns
ns
ns
Receive frame to CRS high
100Mbps
130
600
240
600
150
3200
120
10Mbps
100Mbps
End of receive frame to CRS low
10Mbps
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
End of receive frame to sampled 100Mbps
edge of RXDV
10Mbps
800
ns
t
3
VIH(min)
RXCLK
VIL(max)
t
t
2
t
t
5
1
4
RXD[0:3]
RXDV
RXER
VIH(min)
VIL(max)
RXCLK
t
t
8
9
RXDV
RXD[0:3]
t
t
6
7
CRS
TPRX+-
2002-03-29
Rev.1.2
23
ETC [ ETC ]
