RTL8201BL
8.2 A.C. Characteristics
8.2.1 MII Timing of Transmission Cycle
Shown is an example transfer of a packet from MAC to PHY in MII interface.
Symbol
t1
Description
TXCLK high pulse width
Minimum
Typical
Maximum
Unit
ns
100Mbps
14
20
26
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
140
14
140
200
20
200
40
400
24
260
26
260
ns
ns
ns
ns
ns
ns
t2
TXCLK low pulse width
TXCLK period
t3
t4
TXEN, TXD[0:3] setup to TXCLK 100Mbps
10
5
rising edge
10Mbps
ns
ns
t5
t6
t7
TXEN, TXD[0:3] hold after 100Mbps
10
25
TXCLK rising edge
10Mbps
100Mbps
10Mbps
5
ns
ns
ns
ns
TXEN sampled to CRS high
TXEN sampled to CRS low
40
400
160
100Mbps
10Mbps
100Mbps
10Mbps
2000
140
ns
ns
t8
t9
Transmit latency
60
70
400
170
ns
ns
ns
Sampled TXEN inactive to end of 100Mbps
frame
100
10Mbps
t
3
VIH(min)
TXCLK
VIL(max)
t
t
2
1
t
t
4
5
VIH(min)
VIL(max)
TXD[0:3]
TXEN
TXCLK
TXEN
TXD[0:3]
t
t
6
7
CRS
t
t
8
9
TPTX+-
2002-03-29
Rev.1.2
22
ETC [ ETC ]
