RTL8201BL
6.12 Register 20 PHY 1_1 Register
Address
Name
Description/Usage
Default/Attribute
20:<15:0>
PHY1_1
PHY 1 register (functions as RTL8139C<78>)
R/W
6.13 Register 21 PHY 1_2 Register
Address
Name
Description/Usage
Default/Attribute
21:<15:0>
PHY1_2
PHY 1 register (functions as RTL8139C<78>)
R/W
6.14 Register 22 PHY 2 Register
Address
22<15:8>
Name
PHY2_76
Description/Usage
PHY2 register for cable length test (functions as
RTL8139C<76>)
PHY2 register for PLL select (functions as
RTL8139C<80>)
Default/Attribute
RO
22:<7:0>
PHY2_80
R/W
6.15 Register 23 Twister_1 Register
Address
Name
Description/Usage
Default/Attribute
23:<15:0>
TW_1
Twister register (functions as RTL8139C<7c>)
R/W
6.16 Register 24 Twister_2 Register
Address
Name
Description/Usage
Default/Attribute
24:<15:0>
TW_2
Twister register (functions as RTL8139C<7c>)
R/W
6.17 Register 25 Test Register
Address
25<15:14>
25<13>
Name
Test
Reserved
Description/Usage
Reserved for internal testing
Default/ Attribute
R/W
25:<12:8> PHYAD[4:0] Reflects the PHY address defined by external PHY
address configuration pins
RO
25<7:2>
25<1>
Test
LINK10
Reserved for internal testing
RO
RO
1: Link established in 10Base OK
0: No link established in 10Base
1: Link established in 100Base OK
0: No link established in 100Base
25<0>
LINK100
RO
2002-03-29
Rev.1.2
13
ETC [ ETC ]
