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RTL8100CL-LF 参数 Datasheet PDF下载

RTL8100CL-LF图片预览
型号: RTL8100CL-LF
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
Bit  
R/W  
Symbol  
Description  
15~13  
R/W  
RXFTH2, 1, 0  
Rx FIFO Threshold.  
Specifies the Rx FIFO Threshold level. When the number of received  
data bytes from a packet that is being received into the RTL8100C(L)’s  
Rx FIFO has reached this level (or the FIFO contains a complete  
packet), the receive PCI bus master function will begin to transfer the  
data from the FIFO to the host memory. This field sets the threshold  
level according to the following table:  
000 = 16 bytes  
001 = 32 bytes  
010 = 64 bytes  
011 = 128 bytes  
100 = 256 bytes  
101 = 512 bytes  
110 = 1024 bytes  
111 = No Rx threshold. The RTL8100C(L) begins the transfer of data  
after receiving a whole packet in the FIFO.  
Rx Buffer Length.  
This field indicates the size of the Rx ring buffer:  
00 = 8k + 16 bytes  
01 = 16k + 16 bytes  
10 = 32K + 16 bytes  
11 = 64K + 16 bytes  
12, 11  
10~8  
R/W  
R/W  
RBLEN1, 0  
MXDMA2, 1, 0  
Max DMA Burst Size per Rx DMA Burst.  
This field sets the maximum size of the receive DMA data bursts:  
000 = 16 bytes  
001 = 32 bytes  
010 = 64 bytes  
011 = 128 bytes  
100 = 256 bytes  
101 = 512 bytes  
110 = 1024 bytes  
111 = Unlimited  
7
R/W  
WRAP  
Wraps packet data into the beginning of the Rx buffer.  
0: The RTL8100C(L) will transfer the rest of the packet data into the  
beginning of the Rx buffer if this packet has not been completely moved into  
the Rx buffer and the transfer has arrived at the end of the Rx buffer.  
1: The RTL8100C(L) will keep moving the rest of the packet data into  
the memory immediately after the end of the Rx buffer, if this packet has  
not been completely moved into the Rx buffer and the transfer has  
arrived at the end of the Rx buffer. The software driver must reserve at  
least 1.5 Kbytes buffer to accept the remainder of the packet. We assume  
that the remainder of the packet is X bytes. The next packet will be  
moved into the memory from the X byte offset at the top of the Rx  
buffer.  
This bit is invalid when the Rx buffer is set to 64 Kbytes.  
Reserved.  
6
-
-
Single-Chip Fast Ethernet Controller  
20  
Track ID: JATR-1076-21 Rev. 1.06