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RTL8100CL-LF 参数 Datasheet PDF下载

RTL8100CL-LF图片预览
型号: RTL8100CL-LF
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
 浏览型号RTL8100CL-LF的Datasheet PDF文件第28页浏览型号RTL8100CL-LF的Datasheet PDF文件第29页浏览型号RTL8100CL-LF的Datasheet PDF文件第30页浏览型号RTL8100CL-LF的Datasheet PDF文件第31页浏览型号RTL8100CL-LF的Datasheet PDF文件第33页浏览型号RTL8100CL-LF的Datasheet PDF文件第34页浏览型号RTL8100CL-LF的Datasheet PDF文件第35页浏览型号RTL8100CL-LF的Datasheet PDF文件第36页  
RTL8100C & RTL8100CL  
Datasheet  
Bit  
R/W  
Symbol  
Description  
1
R/W  
VPD  
Set to enable Vital Product Data.  
VPD data is stored in the 93C46 from within offset 40h-7Fh.  
Power Management Enable.  
0
R/W  
PMEn  
Writable only when the 93C46CR register EEM1:0 = [1:1].  
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI  
Configuration space offset 06H.  
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.  
Let C denote the Cap_ID (power management) register in the PCI  
Configuration space offset 50H.  
Let D denote the power management registers in the PCI Configuration space  
offset from 52H to 57H.  
Let E denote the Next_Ptr (power management) register in the PCI  
Configuration space offset 51H.  
PMEn Description  
1: A=1, B=50h, C=01h, D valid, E=0  
0: A=B=C=E=0, D not valid  
5.20. Media Status Register (Offset 0058h, R/W)  
This register allows configuration of device and PHY options, and provides PHY status information.  
Table 20. Media Status Register  
Bit  
R/W  
Symbol  
Description  
7
R/W  
TXFCE/  
Tx Flow Control Enable.  
LdTXFCE  
Flow control is valid in full-duplex mode only. This register’s default  
value comes from the 93C46.  
RTL8100C(L)  
ANE = 1  
Remote  
NWAY FLY mode  
NWAY mode only  
No NWAY  
TXFCE/LdTXFCE  
R/O  
R/W  
R/W  
R/W  
ANE = 1  
ANE = 1  
ANE = 0 &  
full-duplex mode  
ANE = 0 &  
half-duplex mode  
-
-
Invalid  
NWAY FLY mode: NWAY with flow control capability.  
NWAY mode only: NWAY without flow control capability.  
RX Flow control Enable.  
6
R/W  
RXFCE  
Flow control is enabled in full-duplex mode only. The default value  
comes from the 93C46.  
5
4
-
R
-
Reserved.  
Aux. Power present Status.  
Aux_Status  
1: Aux. Power is present  
0: Aux. Power is absent  
The value of this bit is fixed after each PCI reset.  
Single-Chip Fast Ethernet Controller  
24  
Track ID: JATR-1076-21 Rev. 1.06