RTL8100C & RTL8100CL
Datasheet
Bit
R/W
Symbol
Description
6
R/W
FOVW
Rx FIFO Overflow.
Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change.
Set to 1 when CAPR is written but Rx buffer is empty, or when link
status is changed.
Rx Buffer Overflow.
Set when receive (Rx) buffer ring storage resources have been
exhausted.
5
4
3
R/W
R/W
R/W
PUN/LinkChg
RXOVW
TER
Transmit (Tx) Error.
Indicates that a packet transmission was aborted, due to excessive
collisions, according to the TXRR’s setting.
Transmit (Tx) OK.
Indicates that a packet transmission has completed successfully.
Receive (Rx) Error.
2
1
R/W
R/W
TOK
RER
Indicates that a packet has either a CRC error or Frame Alignment
Error (FAE). Collided frames will not be recognized as CRC errors if
the length of the frame is shorter than 16 bytes.
Receive (Rx) OK.
0
R/W
ROK
In normal mode, indicates the successful completion of a packet
reception. In early mode, indicates that the Rx byte count of the
arriving packet exceeds the early Rx threshold.
5.15. Transmit Configuration Register (Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8100C(L). It controls such functions as
Loopback, programmable InterFrame Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Table 15. Transmit Configuration Register
Bit
31
R/W
-
Symbol
Description
Reserved.
-
30~26
R
HWVERID_A
Hardware Version ID A.
Bit3 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
8
0
1
1
1
1
1
1
1
7
0
0
0
1
1
0
1
0
6
0
0
1
0
0
1
0
1
3
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
1
RTL8139
RTL8139A
RTL8139A-G
RTL8139B
RTL8130
RTL8139C
RTL8100
RTL8100B
RTL8100C
RTL8139D
RTL8139C+
RTL8101
1
1
1
1
1
1
0
0
1
1
1
1
0
1
Reserved
Other combinations.
Single-Chip Fast Ethernet Controller
17
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
