RTL8100C & RTL8100CL
Datasheet
Bit
R/W
Symbol
Description
25, 24
R/W
IFG1, 0
InterFrame Gap time.
This field allows the user to adjust the InterFrame Gap time below the
standard: 9.6µs for 10Mbps, 960ns for 100Mbps. The time can be
programmed from 9.6µs to 8.4µs (10Mbps) and 960ns to 840ns
(100Mbps). Note that any value other than (1, 1) will violate the
IEEE 802.3 standard.
The formula for the InterFrame Gap is:
10 Mbps: 8.4µs + 0.4(IFG(1:0)) µs
100 Mbps: 840ns + 40(IFG(1:0)) ns
Hardware Version ID B.
Reserved.
Loopback test.
23, 22
21~19
18, 17
R
-
R/W
HWVERID_B
-
LBK1, LBK0
There will be no packets on the TX+/- lines under the Loopback test
condition. The loopback function must be independent of the link
state.
00: Normal operation
01: Reserved
10: Reserved
11: Loopback mode
16
R/W
CRC
Append CRC.
Setting to 1 means that there is no CRC appended at the end of a
packet. Setting to 0 means that there is a CRC appended at the end of
a packet.
15~11
10~8
-
-
Reserved.
R/W
MXDMA2, 1, 0
Max DMA Burst Size per Tx DMA Burst.
This field sets the maximum size of transmit DMA data bursts
according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
7-4
R/W
TXRR
Tx Retry Count.
These are used to specify additional transmission retries in multiple
of 16 (IEEE 802.3 CSMA/CD retry count). If the TXRR is set to 0,
the transmitter will re-transmit 16 times before aborting due to
excessive collisions. If the TXRR is set to a value greater than 0, the
transmitter will re-transmit a number of times equals to the following
formula before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set
when the transmission fails and reaches to this specified retry count.
Reserved.
3-1
0
-
W
-
CLRABT
Clear Abort.
Setting this bit to 1 causes the RTL8100C(L) to retransmit the packet
at the last transmitted descriptor when this transmission was aborted,
Setting this bit is only permitted in the transmit abort state.
Single-Chip Fast Ethernet Controller
18
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
