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RTL8100CL-LF 参数 Datasheet PDF下载

RTL8100CL-LF图片预览
型号: RTL8100CL-LF
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
5.12. Command Register (Offset 0037h, R/W)  
This register is used for issuing commands to the RTL8100C(L). These commands are issued by setting the  
corresponding bits for the function. A global software reset along with individual reset and enable/disable for  
transmitter and receiver are provided here.  
Table 12. Command Register  
Bit  
7-5  
4
R/W  
-
R/W  
Symbol  
Description  
Reserved.  
Reset.  
-
RST  
Setting to 1 forces the RTL8100C(L) to a software reset state which  
disables the transmitter and receiver, reinitializes the FIFOs, resets  
the system buffer pointer to the initial value (Tx buffer is at TSAD0,  
Rx buffer is empty). The values of IDR0-5 and MAR0-7 and PCI  
configuration space will have no changes. This bit is 1 during the  
reset operation, and is cleared to 0 by the RTL8100C(L) when the  
reset operation is complete.  
3
2
R/W  
R/W  
RE  
TE  
Receiver Enable.  
When set to 1, makes the idle receive state machine active. This bit  
will read back as a 1 whenever the receive state machine is active.  
After initial power-up, software must ensure that the receiver has  
completely reset before setting this bit. This bit will be reset after PCI  
reset deassertion.  
Transmitter Enable.  
When set to 1, and the transmit state machine is idle, then the transmit  
state machine becomes active. This bit will read back as a 1 whenever  
the transmit state machine is active. After initial power-up, software  
must ensure that the transmitter has completely reset before setting  
this bit. This bit will be reset after PCI reset deassertion.  
Reserved.  
1
0
-
R
-
BUFE  
Buffer Empty.  
RX Buffer Empty. There are no packets stored in the RX buffer ring.  
5.13. Interrupt Mask Register (Offset 003Ch-003Dh, R/W)  
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset  
will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to  
cause an interrupt. The Interrupt Status Register bits are always set to 1 if the condition is present,  
regardless of the state of the corresponding mask bit.  
Table 13. Interrupt Mask Register  
Bit  
15  
R/W  
R/W  
Symbol  
SERR  
Description  
System Error Interrupt.  
1: Enable  
0: Disable  
14  
R/W  
TimeOut  
Time Out Interrupt.  
1: Enable  
0: Disable  
Single-Chip Fast Ethernet Controller  
15  
Track ID: JATR-1076-21 Rev. 1.06