Tables
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
Host Interface Signals...................................................................................2-1
Host Signals Not supported by the 82443BX................................................2-3
DRAM Interface Signals................................................................................2-3
Primary PCI Interface Signals.......................................................................2-5
Primary PCI Sideband Interface Signals.......................................................2-6
AGP Interface Signals...................................................................................2-7
Clocks, Reset, and Miscellaneous................................................................2-9
Power Management Interface.......................................................................2-9
Reference Pins ...........................................................................................2-10
Strapping Options .......................................................................................2-11
82443BX Register Map — Device 0 .............................................................3-8
Attribute Bit Assignment..............................................................................3-21
PAM Registers and Associated Memory Segments ...................................3-21
82443BX Configuration Space—Device 1..................................................3-48
Memory Segments and their Attributes.........................................................4-3
SMRAM Decoding ........................................................................................4-7
SMRAM Range Decode................................................................................4-7
SMRAM Decode Control...............................................................................4-7
Host Bus Transactions Supported By 82443BX .........................................4-11
Host Responses supported by the 82443BX..............................................4-12
Host Special Cycles with 82443BX.............................................................4-12
Sample Of Possible Mix And Match Options For 6 Row/3
DIMM Configurations ..................................................................................4-15
Data Bytes on DIMM Used for Programming DRAM Registers..................4-20
Supported Memory Configurations .............................................................4-21
MA Muxing vs. DRAM Address Split...........................................................4-22
Programmable SDRAM Timing Parameters...............................................4-23
EDO DRAM Timing Parameters .................................................................4-23
Low Power Mode ........................................................................................4-31
AGPset Reset .............................................................................................4-32
Reset Signals..............................................................................................4-32
Suspend / Resume Events and Activities ...................................................4-34
SDRAM Suspend Refresh Configuration Modes........................................4-35
82443BX Alphabetical BGA Pin List .............................................................5-4
82443BX Package Dimensions (492 BGA) ..................................................5-9
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
82443BX Host Bridge Datasheet
ix
ETC [ ETC ]
