Architectural Overview
Figure 1-1. Intel® 440BX AGPset System Block Diagram
®
®
Pentium II
Pentium II
Processor
Processor
Host Bus
Video
- DVD
- Camera
- VCR
- VMI
- Video Capture
66/100
MHz
82443BX
Host Bridge
2X AGP Bus
Graphics
Device
Main
Memory
3.3V EDO &
Display
SDRAM Support
Graphics
Local Memory
PCI Slots
Encoder
TV
Primary PCI Bus
(PCI Bus #0)
Video BIOS
System MGMT (SM) Bus
2 IDE Ports
(Ultra DMA/33)
82371EB
(PIIX4E)
(PCI-to-ISA
Bridge)
IO
APIC
USB
USB
2 USB
Ports
ISA Slots
ISA Bus
System BIOS
sys_blk.vsd
Host Interface
The Pentium II processor supports a second level cache via a back-side bus (BSB) interface. All
control for the L2 cache is handled by the processor. The 82443BX provides bus control signals
and address paths for transfers between the processors front-side bus (host bus), PCI bus, AGP and
main memory. The 82443BX supports a 4-deep in-order queue (i.e., supports pipelining of up to 4
outstanding transaction requests on the host bus). Due to the system concurrency requirements,
along with support for pipelining of address requests from the host bus, the 82443BX supports
request queuing for all three interfaces (Host, AGP and PCI).
Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space. Host-initiated
memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable memory space) or
DRAM (including AGP aperture memory). For memory cycles (host, PCI or AGP initiated) that
target the AGP aperture space in DRAM, the 82443BX translates the address using the AGP
address translation table. Other host cycles forwarded to AGP are defined by the AGP address map.
PCI and AGP initiated cycles that target the AGP graphics aperture are also translated using the
AGP aperture translation table. AGP-initiated cycles that target the AGP graphics aperture mapped
in main memory do not require a snoop cycle on the host bus, since the coherency of data for that
particular memory range will be maintained by the software.
1-2
82443BX Host Bridge Datasheet
ETC [ ETC ]
